As the dimensions of semiconductor devices and components continue to decrease, the need for increased alignment control between various layers or features within a single layer of a given sample will continue to increase. In the context of semiconductor processing, semiconductor-based devices may be produced by fabricating a series of layers on a substrate, some or all of the layers including various structures. The relative position of these structures both within a single layer and with respect to structures in other layers is critical to the performance of the devices. Examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to monitor and control one or more semiconductor layer processes. For example, metrology processes are used to measure one or more characteristics of a wafer such as dimension (e.g., line width, thickness, etc.) of features formed on the wafer during a process step, wherein the quality of the process step can be determined by measuring the one or more characteristics. One such characteristic includes overlay error.
An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). If the layers or patterns of a given semiconductor device are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. The misalignment between any of the patterns used at different stages of semiconductor integrated circuit manufacturing is known as ‘overlay error.’
Moreover, if a measured characteristic, such as overlay error, of the wafer is unacceptable (e.g., out of a predetermined range for the characteristic), the measurement of the one or more characteristics may be used to alter one or more parameters of the process such that additional wafers manufactured by the process have acceptable characteristics.
In the case of overlay error, an overlay measurement may be used to correct a lithography process in order to keep overlay errors within desired limits. For example, overlay measurements may be fed into an analysis routine that calculates “correctables” and other statistics, which may be used by the operator in order to better align the lithography tool used in the wafer processing.
In a general sense, metrology applications, such as overlay measurements, require high quality optics in order to satisfy the requirements of advanced lithography processes. In the case of overlay metrology, optical imperfections (e.g., aberrations) in the optical components of an implementing system may result in Tool Induced Shift (TIS). In this manner, optical imperfections in an optical system may cause a shift in the measured overlay relative to the actual overlay. For example, optical aberrations present in an optical column of a metrology may lead to TIS. The standard measurement of TIS involves measuring overlay at first position and then rotating the wafer by 180 degrees and repeating the overlay measurement.
There are, however, a number of disadvantages to using metrology processes and tools to measure one or more characteristics of a wafer for process monitoring and control applications. For example, most metrology tools are relatively slow, particularly compared to inspection systems. Therefore, metrology processes are often performed at one location or a limited number of locations on the wafer such that metrology results may be acquired in a relatively expedient manner. However, many processes used to manufacture semiconductor devices produce wafers that have characteristic(s) that vary across the surface of the wafers. As such, using metrology measurements performed at one location or a limited number of locations on a wafer may not provide sufficient information about the characteristic(s) of the wafers such that the process can be accurately monitored and controlled. Therefore, the sampling plan of the metrology process can significantly affect the meaningfulness and usefulness of the metrology results.
In a practical sense, all optical metrology systems generate tool induced shift to some degree. As such, TIS must be corrected for during semiconductor device fabrication processing, resulting in increased processing times and cost. These inefficiencies are compounded by the fact that a single TIS measurement requires two overlay measurements, a first overlay measurement at zero degree wafer orientation and a second overlay measurement at 180 degree wafer orientation.
Accordingly, it may be desirable to provide a method and/or system which provides a more efficient TIS sampling scheme, allowing for fewer measurements of a selected wafer, while mitigating the loss of measurement information by utilizing an approximation method to provide adequate TIS information for unmeasured sampling locations.